1. Field of the Invention
The present invention relates to a power-on reset used in restoring a storage device, register, or memory to a predetermined state when power is applied. The present invention further relates to digital power-on reset simplifying operation of the device.
2. Description of the Related Art
A power-on reset is used in restoring a storage device, register, or memory to a predetermined state when power is applied. A power-on reset circuit is a necessary circuit for most systems to have. A system generates power-on reset signals to reset all subsystems and to make sure all things are initialized properly. All subsystems, including chips, rely on an external reset signal to reset the chips. In the prior art systems, a dedicated analog circuit is used to generate the reset signal.
The power-on reset circuit detects the power-on condition, and outputs reset signals to reset other circuits. The reset circuit is responsible for generating enough reset time. The output reset signal may last for a sufficient period to make sure all components are properly reset.
FIG. 1 illustrates the behavior of the chip after power-on. When power-on occurs, step 101, the chip detects the reset signal, step 102. If the reset signal is keeping on, the chip will always be in a reset state, step 103. After the reset signal is off, the chip will start chip initialization, step 104, and get into service when initialization is done, in step 105. The power-on reset event should occur only once after power-on.
FIG. 2 illustrates a traditional wire connection between a reset circuit 201 and chips 202. For the reset circuit 201, after the power is on, the reset circuit 201 will detect the condition, and generate a reset cycle to all chips 202. The quality of a reset signal is very important. The reset signal has to be most nearly a square wave. Any instability may cause the system to become locked up. Such instabilities, such as a glitch, will improperly reset the chip.
FIG. 3 illustrates a simple power-on reset circuit. It is an analog circuit and relies on a capacitor C to detect the power-on condition. After the power is on, the capacitor C is not charged, and its voltage is zero. The power VCC will charge the capacitor C through resistor R. Before the capacitor C is fully charged, the circuit has enough time to reset other components 301. A length of the reset time is based on a value of resistor R and capacitor C, i.e. the RC pair. And after capacitor C is fully charged, the reset cycle is also finish. This makes sure the power-on reset event only occur once. The circuit or similar ones are widely used to perform the power-on function, and such a circuit is not costly. Since the output of RC pair is not a perfect square wave, a filter, like a Schmitt trigger, is also integrated into the circuit.
The general flow of a power-on process is illustrated in FIG. 4. In step 401, the power-on event occurs and a reset signal is generated, in step 402. Thereafter, the reset is complete, in step 403, and the process ends.
However, there are drawbacks in the approach. The power-on reset circuit is an analog type circuit, and is not able to be built in digital chip. It can only be installed outside the chips that need to be reset. The chips that need to be reset require a dedicated input pin to get the reset status. The quality of the reset signal is also of concern, since a glitch or any unstable voltage is not permitted. However, the usage of filter can improve the quality of this voltage in the prior art. Thus, there is a need for an improved power-on reset circuit that does not have at least some of the drawbacks discussed above.